1. Field of the Invention
The present invention generally relates to electronic communication between computer components, and more particularly, to a mechanism and method for determining a capability of a various components coupled to a bus.
2. Background of the Invention
Computer systems include a number of modular components with specialized functions that cooperatively interact to realize the many features of modern computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. One of the critical requirements in designing a new computer system is that all system components (including those that may be added to the system by a user) must be compatible. A component is compatible if it effectively communicates and transfers data without interfering with the operation of other system components.
As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a “bus”. As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or through sockets on the main system circuit board (or “motherboard”) that are connected to the system's bus. One early bus that still is in use today is the Industry Standard Architecture (ISA) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A large number of peripheral components have been developed over the years to operate with the ISA protocol.
The components which couple to a given bus receive data from the other components on the same bus via the bus signal lines, and selected components may operate in turn as “bus masters” to send data to other components over the bus. Accordingly, each component on the bus circuit operates according to a protocol associated with that bus which defines the purpose of each bus signal and regulates such parameters as bus speed and arbitration between components requesting bus mastership. A bus protocol also determines the proper sequence of bus signals for transferring data over the bus. As computer systems have continued to evolve, new bus circuits offering heightened functionality have replaced older bus circuits, allowing existing components to transfer data more effectively.
An improved bus architecture called the Extended Industry Standard Architecture (EISA) increased the bus data width to 32 bits, and added a way to exchange data without the assistance of the CPU. The EISA bus protocol permits system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus independently of the CPU.
Currently, the most popular computer bus is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus has bus master capabilities and a 32-bit data path. The PCI bus operates at clock speeds of 33 MHz or faster. Revisions to the PCI bus standard allow for clock speeds up to 66 MHz, and allow a 64-bit data path.
The newest bus architecture, PCI-X, is based on the PCI bus. It has a 64-bit data path, and a clock speed of up to 133 MHz, but remains backward-compatible with conventional PCI components. Thus, PCI-X components can operate at 33 MHz, 66 MHz, and 133 MHz. The PCI-X components may also support 50 MHz and 100 MHz operation to allow multiple components on each segment of the PCI-X bus.
The PCI-X bus offers a raw bandwidth of up to 1 gigabyte per second, making it attractive for high-performance system designers. Such systems may include commercial servers needing an “always-on” capability. In such systems, maintenance is performed while the computers are running, so the components must be “hot-swapped”, i.e. removed and inserted from bus connectors while the computer continues operating.
To benefit such systems, a new specification called “Compact PCI” is being developed to accommodate PCI-X bus- and PCI bus-compatible modules on a mix-or-match basis in an industrially-robust package. However, a challenge exists. How can the various bus components quickly determine the maximum frequency supported by the existing bus configuration, and how can that information be properly conveyed to components added while the system is in operation?